The present invention relates to disc drives. More specifically, the present invention relates to a configuration for a channel-to-controller interface in the disc drive.
A typical disc drive includes one or more discs mounted for rotation on a hub or spindle. A typical disc drive also includes one or more transducers supported relative to surfaces of the discs in the disc drive to read information from, and write information to, the discs. The transducers along with any air bearings associated therewith are collectively referred to as a data head. A drive controller is conventionally used for controlling the disc drive system based on commands received from a host system. The drive controller controls the disc drive to retrieve information from the disc and to store information on the disc.
An actuator operates within a servo system and typically includes an actuator arm that supports a flexure or flexure assembly which, in turn, supports the data head. The actuator moves the data head radially over the disc surface for track seek operations and holds the transducer directly over a track on the disc surface for track following operations.
Information is typically stored on the discs by providing a write signal to the data head to encode information on the surface of the disc representing the data to be stored. In retrieving data from the disc, the drive controller controls the actuator so that the data head flies above the disc, sensing the information on the disc, and generating a read signal based on that information. The read signal is then decoded by the drive electronics to recover the data represented by the information stored on the disc, and consequently represented in the read signal provided by the data head.
In conventional disc drives, user information is provided from a host to a controller circuit where it is stored as bits in a cache buffer. The data are formatted, appended with error correction and detection information and provided to a read/write channel that encodes the data and writes it to the media. During a read operation, the signal stream from the disc is inverse transformed back to user information through a separate read path, some of which resides in the read/write channel circuit and some of which resides in the controller.
All circuits are clocked synchronously such that the data rate at any point in the data path from the input buffer in the controller to the media is a direct transform of the user data rate. Each circuit adds a small delay or latency such that the write data bytes leaving the cache buffer arrive on the disc after a transformation several bit intervals later. The read circuit detection and inverse transformations also add a small delay, usually longer than the write circuit delay, from the disc signal through the read path to the cache buffer.
Future detection and transformation methods will add complexity to the system in an attempt to allow higher areal density of information to be stored on the disc surface. However, the read and write path delays will no longer be small.
Specifically, for example, read path delays with iterative decoding channels can be less than, equal to, or longer than a sector time, where a sector is a minimum unit of user information stored as a separate entity on the disc. Currently, the path delay occurs between sectors. For example, the read decoding path delay occurs during the intersector gap field, and the write encoding path delay occurs during the preamble field. However, as the path delay increases, the unused portion of disc space between sectors increases, resulting in wasted storage space.
To address this deficiency, long latency interfaces decouple the data transfer from the controller circuit to the read/write channel circuit (or between the controller and read/write channel functions if they are implemented on a single physical integrated circuit chip) from the data transfer between the read/write channel circuit (or function) and the disc media. The clocking and data bus requirements of long latency interfaces are different than those for traditional channel-to-controller interfaces and must address many different timing issues.
Embodiments of the present invention address one or more of these and other problems and offer advantages over the prior art.
Embodiments of the present invention illustrate various configurations of the channel-to-controller interface. In one embodiment, width of symbols crossing the interface is fixed, as is the clock rate. In other embodiments, the symbol width is variable, and the clock rate is also varied based upon the size of the interface symbol width and the operation of the channel.
For example, in one embodiment, the symbol width varies based upon the user bit width and based upon the particular functions located in the controller. In other embodiments, the symbol width is set at a fixed bit width, or is fixed at a size based on the particular error correction code symbol width (such as the Reed Solomon code symbol width).
The clock can also be variable and can be based on the number of bits in the user data, the number of bits in the error correction code symbol, the number of bits in the interface symbol, or based on the media clocking speed. Of course, the clock period in these embodiments can be varied as well to accommodate the addition or subtraction of bits by the various functional blocks used in transforming the data in the controller and channel.